Embodiments of the present invention relate to an internal voltage generating circuit, and more particularly, to an internal voltage generating circuit that can reduce the power consumption by controlling a supply voltage driving force according to the level of an interval voltage.
In general, a semiconductor memory device receives a power supply voltage VDD and a ground voltage VSS from an external device to generate an internal voltage necessary for an internal operation. Examples of the voltages necessary for the internal operations of a memory device include a core voltage VCORE supplied to a memory core region, a high voltage VPP used to drive a word line or used in the event of overdriving, and a back-bias voltage VBB supplied as a bulk voltage of an NMOS transistor of a core region.
Meanwhile, a bit line pre-charge voltage VBLP supplied to pre-charge a bit line pair BL/BL in a pre-charge operation and a cell plate voltage VCP supplied to a memory cell are driven by the core voltage VCORE. Thus, a sufficient number of core voltage driving circuits are configured to rapidly supply a current necessary to generate the bit line pre-charge voltage VBLP and the cell plate voltage VCP.
A known core voltage driving circuit drives a core voltage VCORE when performing an active operation, and stops the driving of the core voltage VCORE when not performing the active operation. However, even when the active operation is in progress, if the bit line pre-charge voltage VBLP and the cell plate voltage VCP reach a target level, there is no need to apply the core voltage VCORE in order to generate the bit line pre-charge voltage VBLP and the cell plate voltage VCP. However, even when there is no need to apply the core voltage VCORE in order to generate the bit line pre-charge voltage VBLP and the cell plate voltage VCP, the known core voltage driving circuit continues to drive the core voltage VCORE, thus causing unnecessary power consumption.